short form / Daniel.F.Smith-resume2026-redacted / 2026-07-26

Daniel F. Smith Ph.D. M.A. B.A. Gig Harbor / Pierce County WA ______________________________ ____________________________

Target roles
Senior software engineer seeking hands-on embedded and systems software development roles covering initial concepts to production. Not seeking management positions. Hybrid work preferred.

Profile
Highly experienced in architecture-to-deployment low-level systems, drivers, firmware, and performance-oriented infrastructure for AI accelerators, storage, robotics, and networking. U.S. citizen.

Skills
Architecture, design, and implementation for software and its interface to hardware.

Employment highlights

⊳

NorthPole AI inference processor

Senior Software Engineer, IBM Research, 2020–present

Principal software architect for the PCIe AI accelerator driver stack, enabling hardware/software co-design across runtime, simulator, and first-silicon bring-up. Built around containerized VFIO/QDMA, C++, Linux, and PCIe DMA.

⊳

High-performance storage and robotics

Senior Software Engineer, IBM Research, 2011–2020

Designed real-time servo control on a custom embedded Linux platform, interfacing a high-performance robotic archival system to a cloud object-store. Strong background in real-time C, embedded control, DSP, and systems integration.

⊳

iSCSI, RAID, and flash systems

Senior Software Engineer / Architect, IBM Research, 1997–2010

Built protocols, drivers, and storage-system prototypes across Linux and Windows, including NAND flash evaluation, RAID, and erasure-coding research. Authored the original iSCSI specification (RFC 3720) and implemented the first iSCSI prototypes.

Education

⊳

Ph.D., Information Storage Technology

University of Plymouth, UK, 1993–1997

⊳

M.A. and B.A., Physics and Theoretical Physics

University of Cambridge, UK, 1990–1993

long form / Daniel.F.Smith-resume2026-redacted / 2026-07-26

Daniel F. Smith
Ph.D. M.A. B.A.

Contact:

_____________ (mobile)
______________, Gig Harbor, WA 98329
____________ https://devdot.dev
Offering:

Got an idea? I’ll make it real. An experienced senior engineer and architect, equipped to prototype and deliver cutting-edge projects across the compute stack from electronic hardware to user software control.

Summary:

⊳ 25+ years of experience as a research engineer and architect, focused on the convergence of hardware and software in high-performance A.I. inference, storage systems, robotics, servo control, and networking.

⊳ Physicist by training, with a strong grounding in the physical, statistical, and mathematical sciences.

⊳ Embedded systems, PCIe, networking, Linux/Windows drivers, prototyping, circuit design, user control interfaces and data presentation.

⊳ 36 U.S. patents (80+ worldwide), multiple publications and papers.

⊳ Developed the first iSCSI prototype targets and initiators and wrote the original specification (now RFC 3720).

Skills:

My language of choice is C or C++, with bash as glue, built with make or CMake, stored in git, with Doxygen, supplemented with LaTeX, running on Linux, and tuned with Perfetto. I am comfortable in many systems and languages and pick up new idioms quickly, from tiny microcontrollers to large distributed and mainframe systems. People in the lab often come to me with questions, and my mentoring is sought out.

⊳ Delivered projects in Python, C++, JavaScript/TypeScript (with CSS/HTML and VS Code/Node-like environments), assembler (ARM, DSP), gnuplot, and device drivers for Linux and Windows.

⊳ Libraries and protocols: SCSI, TCP/IP, Ethernet, PCIe, VFIO, IB, USB, SAS, SATA, SPI, I2C, TLS, HTTP, SMTP, DAP, matplotlib, D3, Arduino, and Espressif.

⊳ Hardware experience includes designing circuit boards, setting BGAs, and reworking SMDs of all sizes. I have built 3-phase motor-vector- control servo systems from the ground up.

Passions:

I love making gadgets and repairing things. I get my energy from systems that work flawlessly for years with no maintenance, even when abused, possibly with very heavy boots. When on a project, I will go to incredible lengths today to avoid headaches tomorrow. A discovered fault in any code puts me on a single-minded quest to fix it. My personal professional motto is “Don’t skimp.”

____________________ Résumé of employment ____________________

1997–present:

IBM Research, IBM Almaden Research Center, San Jose, CA

During my post-graduate work, I visited several companies in the magnetic recording industry. Of those places, I chose IBM because it had the untidiest labs, and hence did the most real work.

—2020–present: Senior Software Engineer; NorthPole AI Inference processor.

I was brought in to the world-renowned team that developed the TrueNorth neuromorphic processor, when they wanted to take its successor to the next level. I was tasked with forming the blank sheet design for the SW interface to this new generation of PCIe inference processor, capable of audio, video and language processing.

The NorthPole AI processor achieved an order-of-magnitude improvement in performance and power efficiency over the current state-of-the-art GPU designs. As principal device driver architect and software lead I developed the driver architecture that enabled the runtime subsystem to communicate with the hardware, validation simulator, and Verilog hardware simulator which enabled the team to achieve 22 billion transistors of fully functional silicon on first tape-out without modifying the runtime. Side projects were driving the performance profiling effort, setting up register debugging with DAP and a VSCode extension, and a modular vision pipeline runtime.

For the LLM architectures, the design expanded to utilize direct card-to-card communication over PCIe DMA with 16 cards in an x86 chassis, and Infiniband transport between multiple hosts. Developed without root access through VFIO to Xilinx QDMA (ring buffer) FPGA controllers. Articles were published in Science Magazine and IEEE journals for unprecedented performance and power efficiency. (ML, C++, VFIO, PCIe, IB, VSCode, DAP, OpenCV, Perfetto.)

—2014–2020: Senior Software Engineer; Cloud Data Architecture. Robotic active archive.

Our team built a very high performance robotic Blu-ray disc (BD-XL) storage system on my hardware/software servo platform, and made it resilient as a cloud object store. We collaborated with a Japanese company to produce a system designed to compete with disk, and still recover the data from 6ft of floodwater.

—2011–2014: Senior Software Engineer. Robot cars!

Tape storage has a problem: it’s slow for random access. We designed a high-performance semi-autonomous robot car as a demonstrator of several new technologies and possible product. The vehicle (about 6 inches long) could accelerate over a plane at about 3g, and deliver any tape (diameter of a quarter) to a high-speed tape unit, running a request-to-data cycle time of about 10 seconds, compared with 300 seconds in a contemporary tape system. I designed the robot electronic hardware, developed and coded an entire servo operating system as a single SoC design (AM335X), pulling in dual cameras, 3-phase motor control and high-speed data capture.

—2008–2010: Senior Software Engineer. NAND flash.

Study of NAND flash memory devices for use in reliable storage systems. As the price of flash memory decreased, so did the quality of the devices, moving from SLC to MLC (and now TLC and QLC). We were tasked with evaluating flash devices and designing mitigation strategies in the form of error correction codes, targeted wear leveling, and new block coding. We worked with a Taiwanese company to modify an existing device to work as a test bed. This code, data and infrastructure is still an ongoing product.

—2005–2007: Senior Research Engineer; Advanced File Architecture. Next generation RAID.

This project involved the implementation of a prototype advanced RAID system, taking it to a product turnover stage and then shopping it to venture capital companies. It was never funded, but the advanced features we prototyped are only just coming to the enterprise market a decade later. It used real-time load balancing and a highly resilient coding scheme (3+3), with the object of making the probability of data loss due to failure arbitrarily small. This has involved studies on reliability and performance, security, maintenance, discovery modeling, and engineering back end device drivers to connect to existing operating systems.

—2002–2005: Software Architect. Erasure coding and simulation.

I started a study of new erasure correction codes, and their simulation and performance implementation in current CPU architectures, and enterprise storage systems. From this work, two standouts are DOiNKS (Device Operating in Non-Kernel Space): a system for rapidly prototyping RAID architectures in Windows user space; and the Shotgun Simulation: a graphical representation of what data recovery operations would happen if you fired a shotgun at a storage system. The enhanced Blaum codes we developed with Winograd were sufficiently complex that a graphical representation was almost a necessity.

—1999–2002: Advisory Software Engineer. Internet SCSI.

I was the key architect implementing the first experimental iSCSI protocol prototypes under Linux and Windows at IBM. I was instrumental in first demonstrating the need for block network storage to IBM, to laying out the bits in the TCP stream, then presenting the work with colleagues to the IETF standards body and delivering working code to the product development team. Patents were filed in key areas, and I was also presented with an Outstanding Technical Achievement Award for this work.

I had the opportunity to manage small groups of summer interns on two occasions. In 2001, we built a DVD player that plays movie discs over the network (hardware, FPGA and software design). In 2000, our team built the first Windows 2000 iSCSI initiator, and we implemented Kerberos authentication in the nascent iSCSI protocol.

—1997–1999: Visiting Scientist. Hard disk drives and RAID6.

worked on several exploratory research storage projects, including building the prototype EVENODD class RAID6 array, making mechanical disk drive measurements to determine dynamic interactions and developing an interface control library. I also tuned high-performance TCP over the new gigabit ethernet technology. IBM (later HGST) published my Power Booster software to control the power saving features of mobile hard disk drives.

1993–1997:

Ph.D., Centre for Research in Information Storage Technology,
University of Plymouth, UK

My doctorate in the CRIST group was centered on the construction and modification of modern signal processing methods with the standard credit card magnetic stripe. I designed and built new PC hardware for card processing (housing cutting-edge multi-track MR read/write heads and circuitry), new codes, new testing methods and new detection and synchronization methods to boost the card’s storage capacity 100-fold.

I architected an Internet Service Provision system communicating over a satellite television audio subcarrier for the Satellite Communications Research Centre. I was responsible for developing for the ISP PPP stack, and client NDIS network drivers. This system was deployed in Jordan.

1990–1993:

M.A. and B.A., Physics and Theoretical Physics,
University of Cambridge, UK.

This course awarded both Master and Bachelor of the Arts qualifications. My final year project involved constructing capture hardware and writing software from scratch to connect to a radio telescope to an 8086 PC. This real-time system then listened to a (very) noisy pulsar source over a 12 hour period and determined its frequency to six significant figures. My professor was startled to see that it worked the first time out at the telescope.

In the Cambridge Computer Society, I coded a mini-operating system for placing a microprocessor-based teletext decoder onto the IBM mainframe; and was the Magnetic Media Supply Executive.

I worked vacations at a power station where I threaded thermocouples into nuclear fuel, built and installed a voice communication system and designed several database applications.

1987–1990:

Sixth Form College, Kings of Wessex Upper School, Cheddar, UK.

I wrote a real-time FFT spectrum analyzer in ARM2 assembly code. I digitized the surface of a coin using a hand-made linear transformer scanning probe with custom software and PWM drivers in ARM assembler. I wrote a specialty printer driver and managed the Physics Software library for the County of Somerset Education Department.

‘A’ levels (age 18): Maths (A), Further Maths (A), Physics (A), Chemistry (A).

‘O’ levels & GCSE (age 16): Technology (A), English (A), English Lit. (B), Biology (A), Geography (A), German (A)

____________________ Published work ____________________

US Patents:

10,580,451 10,529,371 10,438,629 10,242,705 10,186,295 10,127,941 9,990,325 9,984,722 9,928,008 9,741,389 9,741,390 9,690,492 9,672,863 9,633,686 9,373,353 9,058,291 8,941,936 8,656,088 8,645,619 8,583,868 8,484,408 8,386,891 8,214,684 8,108,750 7,912,918 7,899,881 7,788,569 7,783,783 7,702,853 7,562,281 7,533,325 7,379,974 7,281,177 7,254,754 7,134,139 7,010,645

Publications:

⊳ SCSI/TCP (SCSI over TCP), Satran et al, IETF Internet Draft, Feb. 2000. (Now RFC 3720: iSCSI.)

⊳ Neural inference at the frontier of energy, space, and time, D. S. Modha et al., Science 382, 329–335 (2023).

⊳ Enhanced Coding, Clock Recovery and Detection for a Magnetic Credit Card, Thesis, University of Plymouth, UK (1998)

Papers:

⊳ The NorthPole Validator: A Cycle-Accurate Simulator for HW/SW Codesign of a Prescheduled Neural Inference Accelerator, A. Andreopoulos et al., 2025 IEEE HPEC (2025).

⊳ Breakthrough Low-Latency, High-Energy-Efficiency LLM Inference Performance Using NorthPole, R. Appuswamy et al., 2024 IEEE HPEC (2024).

⊳ Breakthrough Edge AI Inference Performance Using Northpole in 3U VPX Form Factor, F. Akopyan et al., 2024 IEEE HPEC (2024).

⊳ 11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip, A. S. Cassidy et al., 2024 IEEE ISSCC (2024).

⊳ IBM NorthPole Neural Inference Machine, D. S. Modha et al., 2023 IEEE Hot Chips (2023).

⊳ A Fixed Sample Rate Bayesian Detector in a Variable Speed Magnetic Channel, IEEE Transactions on Magnetics, Vol. 33, No. 5, Sep. 1997, pp. 2797–2799; presented at Intermag 97.

⊳ High Density Storage on a Magnetic Stripe Card, IEEE Transactions on Magnetics, Vol. 32, No. 5, Sep. 1996, pp. 4025–4027; presented at Intermag 96.

⊳ Non Linear Magnetoresistance, Mapps et al, Studies in Applied Electromagnetics and Mechanics (ISSN 1383–7281), Nonlinear Electromagnetic Systems (A.J. Moses and A. Basak Eds.), IOS Press 1996, pp. 628–633.

⊳ The Development of an Operational Satellite Internet Service Provision, Smithson et al, IEEE Globecom, Nov. 1997, pp. 1147–1151.

____________________ Additional ____________________

Personal:

My interests include computing (I run a high-availability cluster in a full rack in my garage, ask me about my fibre network), photography and imaging, telephony (ask me about my toll-free number), orchestral and concert recording (designing and modifying microphones and pre-amps, and mixing in post), combining embedded CPUs with antique technology (1960s time-sync clocks). I ride my sport motorcycle whenever possible, and I have rebuilt an automobile engine.

My amateur radio callsign is AG6TI and I used to be a control operator for our local repeater in California where I liaised with the City of San Jose Emergency Services to provide emergency wireless coverage.

I was treasurer for a non-profit for five years, responsible for cleaning up the lackluster record-keeping and filing the annual Form 990.

I was chosen as the recipient of the American Cancer Society (Silicon Valley) Excellence in Volunteerism Award for my accounting and A/V support.

I am occasionally seen singing opera on stage: but that’s another résumé!